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Improv Systems -- Configurable IC Architecture
 
Founded: Jul 1997
Status: Private
Issue(s): 6/99
www.improvsys.com
100 Cummings Center-Suite 343G
Beverly, MA 01915
Tel: 978-927-0555
Fax: 978-927-0999

Improv was founded in July 1997 to develop configurable IC architectures, compilers, system applications and support technology for the semiconductor market. Improv’s goal is “to make the PSA an attractive and highly efficient platform upon which a vast array of innovative applications can be written.” The company has raised about $9 million from angel investors to date. About $5-8 million will be sought in Q1 from private investors and corporate partners. Improv has about 26 employees.

Systems-on-chip is basically an evolution of board design onto silicon. Standard components are replaced by “virtual components” or on-chip cores and megacells. Improv believes that core-based design methodologies are not going to reduce today’s 6-15 month development cycle.

Improv’s Programmable System Architecture (PSA) configurable platform allows chips to be customized through software components rather than through custom hardware. The Improv Platform is a configurable chip (or megacell) which provides high performance and high capacity coupled with extremely quick time-to-market. Unlike IP cores, the platform provides the capability to define custom, application-specific functionality and map that onto Improv’s chip. The PSA is a modular collection of predefined processing engines. These engines incorporate Very Long Instruction Word (VLIW) technology and a high degree of concurrency. Each engine is programmable through software loaded onto on-chip memory.

The methodology allows engineers to define or re-use application software components (VirtualIP) using the Improv Application Framework to describe their application. These applications are mapped into instructions for the various processing engines on the PSA by the PSA Compilation System. This methodology is similar to the host-based processing paradigm, however Improv claims that its architecture is much more effective for embedded solutions than the traditional Von-Neumann/Harvard architecture of most processor-based systems.

The PSA consists of multiple on-chip processors, VLIW instruction parallelism, and an advanced compilation system. PSA-based designs are claimed to take 15% of the time and 5% of the cost of the current electronic system design process. The PSA solution includes a component based Java application development framework, a compilation system and the PSA configurable architecture. PSA solutions allow design teams to define Java programs to configure Improv’s predefined ICs into virtualASICs tailored to their application needs, dramatically decreasing time-to-market.

The PSA Application Development Framework is a system-level semantic framework for describing applications as a collection of concurrent, communicating tasks. Each task is encapsulated into an object/component with an explicitly defined interface. Data which is shared between tasks is encapsulated into “data managers.” It borrows many concepts of instantiation, interface definition and hierarchical, structural connectivity from HDLs.

Improv’s approach is claimed to provide the performance and capacity of an ASIC due to VLIW task processors, concurrent processing and system integration. Integrated hardware/software mapping, full Java program analysis (execution, memory and scheduling) and programmable I/O behavior provides the programmability and flexibility of an embedded processor.

Jazz is the first family of PSA-based ICs. Heterogeneous task engines are optimized for different types of tasks. Computation intensive tasks can be mapped onto task engines with ALUs and multipliers in the data path. Simple tasks can be mapped onto simple data path task engines. Each task engine is programmed with a unique VLIW instruction set, which can be used to directly program the flow of data through the data path.

The application development kit provides all the pieces needed to define and verify applications to be mapped onto a PSA chip. The Application Framework is a Java class library that defines a series of classes, interfaces and utilities used to describe VirtualIP and VirtualASSP objects and test benches for them. The Solo Compilation System optimally maps an application onto a PSA chip. The Notation Developer’s Environment and Simulator is a graphical development environment, which augments the host Java environment for developing and debugging applications before and after compilation. VirtualIP Component Libraries are sets of predefined VirtualIP components, written in Java, that can be used as-is, or as a starting point for application and test bench development.

The PSA is targeted at consumer electronics and communications markets. Improv is developing a series of reference designs that define a complete, production-ready chip specification. The Improv business model is non-exclusive licensing of its PSA Architecture and development tools to semiconductor vendor partners. Improv also provides virtualIP and virtualASSP libraries to streamline the application development process. Competitors include Equator, BOPS, Cognigine, and custom ASICS, to name a few. Improv believes its key advantages are its use of heterogeneous resources and silicon efficient compiler, which is easy to use and exposes concurrency in the devices.

Cary Ussery, President & CEO, Founder (formerly the Group Director of Core Technology for Cadence’s Alta Business Unit. He is the co-author of VHDL: Hardware Description and Design and has published over 15 papers on electronic design, electronic applications and IP)

Oz Levia, CTO, Founder (formerly the Director of IP Programs for Cadence’s Alta Business Unit)

Diane Flynn, VP of Business Development and Marketing, Founder (formerly a Project Manager for Group Development at HP’s Medical Products Group)

Ray Ryan, Chief Architect, Founder (formerly the lead technologist for IP modeling and integration methodologies for the Alta Business Group of Cadence)

Alex Wu, VP of engineering (formerly Director of System Engineering and Integration Group at Microtec Research. He also managed the Compiler Development Group at MIPS and was an early member of the team that designed the SPARC architecture)

Russell Priebe, Director, Applications Development (formerly a Senior Engineer with Fastman)

R&D
1485 Saratoga Ave., Suite 100
San Jose, CA 95129
phone: (408) 517-4790 fax: (408) 517-4799



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