Three engineers formed Tak’Asic in 1991 as an ASIC design house. In 1994, Tak’Asic developed JBIG and JPEG expertise, with the partnership of France Telecom. Tak’Asic now provides highly integrated, standard-based digital still image compression solutions. Tak’Asic recently secured EUR 10.8 million in second round financing. Sofinnova Partners and Doughty Hanson Technology Ventures led the round. Initial investors Innovacom, Ventech and SPEF Venture also participated in the round, which was orchestrated by the NetsCapital investment bank. The company has 25 employees.
Tak’Asic is now a fabless provider of still-image compression processing chipsets. Target applications include scanners, laser printers, inkjet printers, fax, digital copiers and multi-function peripherals.
The Tak’B3 chip is claimed to be the fastest JBIG/G3/G4 codec. The device can code or decode a 600 dpi US letter sized CMYK color image in less than 1.5 seconds. The device also implements special Printer/Copier/Fax/MFP operations such as direct compression/decompression of CMYK multiplan images, automatic conversion between G3/G4 and JBIG formats and automatic scaling of the coded image to the printer paper size.
Since the launch of the Tak’B3 chip, Tak’Asic has posted more than 20 design wins with major US, Japanese and Taiwanese manufacturers. Tak’Asic expects revenues to grow at a CAGR of 260% over the next three years, largely driven by market growth in imaging technology.
Jean-Paul Verniere, Chairman and CEO
Bruno Paucard, President and COO
44 Montgomery Street, Suite 630
San Francisco, CA 94104
Tel: 415/362-4477, Fax: 415/362-4478