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Bluespec -- SystemVerilog-based Synthesis Tools
 
Founded: Jun 2003
Status: Private
Issue(s): 12/03, 1/0
www.bluespec.com
200 West Street, Suite 402
Waltham, MA 02451
Tel: 781/250-2200
Fax: 781/250-2011

Bluespec was founded in June 2003 “to manufacture an industry standards-based EDA toolset that significantly raises the level of abstraction for hardware design while retaining the ability to automatically synthesize high quality RTL, without compromising speed, power or area.” Bluespec was incubated within Sandburst where Rishiyur Nikhil led the Bluespec technology team since 2000. The company has secured $4 million in first round funding from Atlas Venture and North Bridge Venture Partners. Bluespec has 20 employees.

Functional logic errors represent 43% of first spin SoC failures and 61% of new ICs require at least one re-spin, according to a survey by Synopsys. Verilog and VHDL design levels are simply too low for today’s complex multi-million gate designs. As a result, verification costs have skyrocketed.

To address this problem, the EDA industry has proposed two different types of solutions, neither fully addressing these issues, according to BlueSpec. One approach has focused on simulation speed, testbench creation and verification environments to make it easier to verify complex designs. However, the growth in design complexity has outpaced the benefits provided by these tools.

The second approach, based on behavioral synthesis or C/C++, has attempted to raise the abstraction level of design expression. Yet this approach has been unable to connect the higher-level model automatically to efficient RTL. These synthesis solutions are overly ambitious and are generally poor at synthesizing control logic.

Bluespec intends to offer the first SystemVerilog-based EDA toolset for ASIC and FPGA designers to automatically synthesize RTL hardware implementations from high-level design descriptions, according to the company. Bluespec’s SystemVerilog-based high-level synthesis toolset delivers high-level design abstraction and full hardware synthesis. From the same source, it compiles both “no compromise” RTL and a cycle-accurate C model for simulation. It synthesizes control logic for “correct-by-construction” design.

The Bluespec high-level hardware design synthesis solution enables:

• more concise, efficient design expression backed by comprehensive static verification,

• better designs, with architectural changes possible throughout the design cycle,

• IP creation, maintenance and deployment,

• high-quality RTL generation, “without compromise,”

• and single source for both RTL and cycle accurate ‘C’ simulation.

Bluespec’s toolset shortens the time to a verified netlist by as much as 50% and eliminates the majority of design errors that typically extend design cycles. In a comparison with a 1.5 million gate ASIC coded in Verilog, Bluespec demonstrated a 13x reduction in source code, a 66% reduction in verification bugs, equivalent speed/area performance, and additional design space exploration within time budgets.

Bluespec’s Assertion-Based Synthesis Toolset leverages patented technology developed at MIT and the emerging SystemVerilog standard.

Based on SystemVerilog, the Bluespec design environment is natural and familiar for describing hardware. In contrast, the execution model of traditional programming languages like C and C++ are very distant from hardware, making it harder to compile good hardware and making it harder for designers to retain their intuitions about the relationship between source code and good hardware.

At the heart of Bluespec’s product is the novel application of Term Rewriting Systems (TRS), a well understood computer science concept, to hardware synthesis – a patented technology developed at MIT by Arvind, the Johnson Professor of Computer Science and Engineering and also a co-founder and member of Bluespec’s board. Research specific to Bluespec at MIT by Arvind, his colleagues and students has included the application of TRS to hardware description, compilation of TRSs to high-quality RTL, formal verification through mathematical transformation (“correct by construction”) and very high-level declarative languages.

TRS can be used to model atomicity, which is a mechanism for reasoning about the functional correctness of highly concurrent systems. TRS also provide an excellent basis for producing designs that are correct-by-construction.

A TRS consists of “terms” which describe hardware states, and “rules” which describe behavior. A “rule” captures both a state-change (an “action”) and the conditions under which it can occur. As the rules in a TRS have atomic semantics, analysis of hardware can be done even though it may be highly concurrent and complex.

In conjunction with TRS-based synthesis, Bluespec employs the emerging SystemVerilog language to create an industry standards-based design environment that raises the level of abstraction for hardware design while retaining the ability to automatically synthesize high quality RTL. The combination of SystemVerilog and TRS permits the Bluespec designer to express very complex hardware structures succinctly and robustly, and still produce optimal, efficient RTL code.

Bluespec wraps the TRS model inside SystemVerilog and toolset that includes:

• efficient static elaboration, including parameterization and higher-order functions

• strong static verification, including expressive types with polymorphism

• hardware modules, bit vectors and bit operations, TRS rules and actions

• and powerful synthesis, capable of complex control logic generation.

Bluespec claims to be unique in using TRS as its model of hardware. TRS’s scalability enables the synthesis of large designs, without being swamped in state explosions and race conditions. In Bluespec, all state elements are explicitly defined by the designer – Bluespec automates hardware generation, not design choices.

Bluespec’s submission for enhancing SystemVerilog design has been formally accepted by the Technical Committee of the Accellera standards organization. The submission addresses Tagged Unions and Pattern Matching for SystemVerilog 3.1a, the latest version of the design language being readied for release in June 2004. The new elements raise the level of abstraction for design and improve the expressiveness and readability of the SystemVerilog language.

Bluespec’s customers are system, silicon, IP and design services companies with requirements for developing complex ASIC and FPGA designs. The company is continuing product development while engaging with its first set of customer projects and has targeted Q1’04 for product availability.

Shiv Tasker, co-founder, President & CEO (previously president and CEO of Phase Forward and SVP of Worldwide Sales, Consulting Services and Corporate Marketing at Viewlogic)

Rishiyur Nikhil, Ph.D., co-founder & CTO (Since 2000 Nikhil led the Bluespec technology team at Sandburst)

Don O’Rourke, Director of Sales (previously Managing Director, Eastern North America for Chartered Semiconductor and Director of Field Operations, Eastern North America for Chronologic Simulation, which was acquired by Viewlogic)

George Harper, Director of Marketing (previously Director of Marketing at Trebia Networks)



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